FPGA-based Speeded Up Robust Features


We present an implementation of the Speeded Up Robust Features (SURF) on a Field Programmable Gate Array (FPGA). The SURF algorithm extracts salient points from image and computes descriptors of their surroundings that are invariant to scale, rotation and illumination changes. The interest point detection and feature descriptor extraction algorithm is often used as the first stage in autonomous robot navigation, object recognition and tracking etc. However, detection and extraction are computationally demanding and therefore can't be used in systems with limited computational power. We took advantage of algorithm's natural parallelism and implemented it's most demanding parts in FPGA logic. Several modifications of the original algorithm have been made to increase it's suitability for FPGA implementation. Experiments show, that the FPGA implementation is comparable in terms of precision, speed and repeatability, but outperforms the CPU and GPU implementation in terms of power consumption. Our implementation is intended to be used in embedded systems which are limited in computational power or as the first stage preprocessing block, which allows the computational resources to focus on higher level algorithms.

Due to several requests on our implementation, we have prepared this webpage, where you can download the FPGA-based SURF.

Speeded Up Robust Features

"SURF: Speeded Up Robust Features" is a performant scale- and rotation-invariant interest point detector and descriptor. It was originally presented at the ECCV 2006 Conference in Graz. More on the original SURF algorithm can be read on SURF pages and in the paper:

Andreas Ess, Tinne Tuytelaars, Luc Van Gool, "SURF: Speeded Up Robust Features", Computer Vision and Image Understanding (CVIU), Vol. 110, No. 3, pp. 346--359, 2008.

Although fast and efficient, it still takes a lot of processing time of standard computers and therefore the authors presented a GPU version as well.

FPGA-based Speeded Up Robust Features

We have been working on an FPGA implementation of the SURF algorithm since the beginning of 2009. The outcome of our work has been presented the IEEE TePRA Conference in Boston 2009 in a paper:

Svab, J., Krajnik, T., Faigl, J., and Preucil, L. (2009). FPGA-based speeded up robust features. In 2009 IEEE International Conference on Technologies for Practical Robot Applications [CD-ROM]. Boston: IEEE, 2009, p.35-41. ISBN 978-1-4244-4992-7.

The full version of the paper is here. Note that this article is protected by IEEE copyright. For the purpose of referencing, use this bibtex entry.


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